Typical test methods for checking whether a semiconductor integrated circuit is acceptable or not are a stored test method and a built-in self-test method (BIST). In the stored test method, a test pattern for an assumed fault is obtained according to an algorithm and applied to the circuit to be tested through a test device which stores the pattern for comparison of response pattern from the circuit with an expected pattern. In the BIST method, the semiconductor integrated circuit incorporates a pseudo-random pattern generator and a signature analyzer to give a huge volume of pseudo-random patterns to the circuit to be tested and compare the compacted result of response pattern with an expected pattern.
The stored test method has the following problem: in order to achieve a high fault coverage for a large-scale circuit to be tested, the required number of test patterns or the required volume of test data is too large for the semiconductor integrated circuit test device to store such patterns or data. The problem of the BIST method is that, since pseudo-random patterns generated by a linear feedback shift register (LFSR) are used, the required volume of test data is relatively small but a high fault coverage cannot be guaranteed when a limited number of pseudo-random patterns are used for a large-scale circuit.
Many proposals for improvement in the fault coverage by the BIST method have been made. In the test point insertion methods disclosed in J-P-A-No. 197601/1998 and J-P-A-No. 142481/1999, a circuit called a test point is added to the circuit under test to achieve a high fault coverage even with random patterns. According to the procedure described in a paper by K. H. Tsai et al, entitled “STARBIST: Scan Autocorrelated Random Pattern Generation” (literature: Proceeding of Design Automation Conference '97. 1997, pp. 472-477), in order to generate neighborhood patterns each of which has one bit flipped with respect to a reference pattern with a specific probability, a circuit which controls the weight of random patterns generated by an LFSR and a circuit which controls bit-flipping are added midway in a scan chain for efficient fault detection. According to the method described in a paper by G. Kiefer et al, “Deterministic BIST with Multiple Scan Chains” (literature: Proceeding of International Test Conference '98. 1998 pp. 1057-1064), a logic for flipping some bits is added in order to transform pseudo-random patterns generated by an LFSR into similar test patterns. In the Reseeding technique stated in a paper by S. Hellebrand, “Generation of vector patterns through reseeding of multiple-polynomial linear feedback shift registers” (literature: Proceeding of International Test Conference '92. 1992, pp. 120-129), LFSR's initial value (called “seed”) is calculated from a test pattern to be generated and the seed is replaced one after another.
All the above-mentioned BIST-based methods for fault coverage improvement have problems to be solved when they are applied to large-scale semiconductor integrated circuits. The test point insertion method has the following two problems: one is that the circuit operating speed is slowed because a test point is inserted into the path in the semiconductor integrated circuit to be tested (hereinafter called a “circuit under test” or “CUT”) and the other is that, since the test point should depend on the CUT, the layout and wiring pattern of the CUT cannot be determined even locally until where to insert the test point is determined, and thus the period of semiconductor integrated circuit design may be prolonged.
The methods proposed by K. H. Tsai et al and G. Kiefer et al have not only the problem of a prolonged design period because the layout or wiring pattern cannot be determined without modifying the circuit which controls bit-flipping or the like depending on the result of test pattern generation (a time consuming process), and the scan chain, but also the problem that, for a large-scale CUT, the method by H. Tsai et al has a restriction on the way of scan chain arrangement, thereby increasing the overhead of wirings, while, in the method by G. Kiefer et al, the bit flipping control circuit must be increased. Regarding the Reseeding technique, although it has no problem of hardware overhead or a prolonged design period in comparison with the original BIST method, the number of seeds is expected to be equal to or larger than the number of stored patterns and thus the main objective of the BIST method, reduction of test data, is not satisfactorily achieved.